? semiconductor components industries, llc, 2001 january, 2001 rev. 4 1 publication order number: mc100lvel30/d mc100lvel30 3.3vecl triple d flip-flop with set and reset the mc100lvel30 is a triple masterslave d flip flop with differential outputs. data enters the master latch when the clock input is low and transfers to the slave upon a positive transition on the clock input. in addition to a common set input individual reset inputs are provided for each flip flop. both the set and reset inputs function asynchronous and overriding with respect to the clock inputs. ? 1200 mhz minimum toggle frequency ? 450 ps typical propagation delays ? esd protection: >2 kv hbm ? the 100 series contains temperature compensation. ? pecl mode operating range: v cc = 3.0 v to 3.8 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 3.0 v to 3.8 v ? internal input pulldown resistors ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 347 devices http://onsemi.com marking diagram* 1 20 a = assembly location wl = wafer lot yy = year ww = work week so20 dw suffix case 751d 100lvel30 awlyyww 1 20 device package shipping ordering information mc100lvel30dw so20 38 units/rail mc100lvel30dwr2 so20 1000 units/reel *for additional information, see application note and8002/d
mc100lvel30 http://onsemi.com 2 d1 logic diagram and pinout: 20-lead soic (top view) r0 r1 d2 17 18 16 15 14 13 12 4 3 5678 9 q0 11 10 v cc q1 q1 v cc q2 q2 v ee d0 19 20 2 1 v cc q0 clk0 clk1 s012 clk2 r2 d r s q q d r s q q d r s q q warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. r l l h l h truth table s l l l h h d l h x x x clk z z x x x q l h l h undef z = low to high transition x = don't care q h l h l undef pin description function ecl data inputs ecl reset inputs ecl clock inputs ecl common set input ecl differential data outputs positive supply negative supply pin d0d2 r0r2 clk0clk2 s012 q0q2; q0q2 v cc v ee maximum ratings (note 1.) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 to 0 v v ee necl mode power supply v cc = 0 v 8 to 0 v v i pecl mode input voltage v ee = 0 v v i v cc 6 to 0 v i c ode u o age necl mode input voltage ee 0 v cc = 0 v i cc v i v ee 6o0 6 to 0 v i out output current continuous surge 50 100 ma ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to am- bient) 0 lfpm 500 lfpm 20 soic 20 soic 90 60 c/w c/w q jc thermal resistance (junction to case) std bd 20 soic 30 to 35 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur.
mc100lvel30 http://onsemi.com 3 lvpecl dc characteristics v cc = 3.3 v; v ee = 0.0 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 62 55 62 55 64 ma v oh output high voltage (note 2.) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mv v ol output low voltage (note 2.) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mv v ih input high voltage 2135 2420 2135 2420 2135 2420 mv v il input low voltage 1490 1825 1490 1825 1490 1825 mv i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. lvnecl dc characteristics v cc = 0.0 v; v ee = 3.3 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 62 55 62 55 64 ma v oh output high voltage (note 2.) 1085 1005 880 1025 955 880 1025 955 880 mv v ol output low voltage (note 2.) 1830 1695 1555 1810 1705 1620 1810 1705 1620 mv v ih input high voltage 1165 880 1165 880 1165 880 mv v il input low voltage 1810 1475 1810 1475 1810 1475 mv i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts.
mc100lvel30 http://onsemi.com 4 ac characteristics v cc = 3.3 v; v ee = 0.0 v or v cc = 0.0 v; v ee = 3.3 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency 1.2 1.2 1.2 ghz t plh t phl propagation delay clk to output s, r 460 470 690 710 480 490 710 730 500 515 730 755 ps t s t h setup time hold time 150 200 0 100 150 200 0 100 150 200 0 100 ps t rr set/reset recovery 400 200 400 200 400 200 ps t pw minimum pulse width clk set, reset 400 650 400 650 400 650 ps t jitter cycletocycle jitter tbd tbd tbd ps t r t f output rise/fall times q (20% 80%) 280 550 280 450 550 280 550 ps 1. v ee can vary 0.3 v. v tt = v cc 2.0 v figure 1. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device q qb d db 50 50 v tt resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1560 low voltage eclinps spice modeling kit an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc100lvel30 http://onsemi.com 5 package dimensions so20 dw suffix plastic soic package case 751d05 issue f 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition.
mc100lvel30 http://onsemi.com 6 notes
mc100lvel30 http://onsemi.com 7 notes
mc100lvel30 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc100lvel30/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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